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integrated circuit systems, inc. general description features ICS9148-08 block diagram frequency generator & integrated buffers for pentium/pro tm 9148-08 rev a 092297p pin configuration ? 3.3v outputs: sdram, pci, ref, 48/24 mhz ? 2.5v or 3.3v outputs; cpu, ioapic ? 20 ohm cpu clock output impedance ? 20 ohm pci clock output impedance ? skew from cpu (earlier) to pci clock - 1 to 4 ns, center 2.6 ns. ? no external load cap for c l =18pf crystals ? 250 ps cpu, pci clock skew ? 400ps (cycle to cycle) cpu jitter ? smooth frequency switch , with selections from 50 to 83.3 mhz cpu. ?i 2 c interface for programming ? 2ms power up clock stable time ? clock duty cycle 45-55%. ? 48 pin 300 mil ssop package ? 3.3v operation, 5v tolerant input. 48-pin ssop power groups vdd1 = ref (0:1), x1, x2 vdd2 = pciclk_f, pciclk(0:5) vdd3 = sdram (0:11), supply for pll core, 24mhz, 48mhz vddl1 = ioapic vddl2 = cpuclk (0:3) * internal pull-up resistor of 240k to 3.3v on indicated inputs the ICS9148-08 generates all clocks required for high speed risc or cisc microprocessor systems such as intel pentiumpro or cyrix. eight different reference frequency multiplying factors are externally selectable with smooth frequency transitions. features include four cpu, seven pci and twelve sdram clocks. two reference outputs are available equal to the crystal frequency. plus the ioapic output powered by vddl1. one 48 mhz for usb, and one 24 mhz clock for super io. spread spectrum built in 1.5% modulation to reduce the emi. serial programming i 2 c interface allows changing functions, stop clock programing and frequency selection. rise time adjustment for vdd at 3.3v or 2.5v cpu. additionally, the device meets the pentium power-up stabilization, which requires that cpu and pci clocks be stable within 2ms after power-up. it is not recommended to use i/o dual function pin for the slots (isa, pci, cpu, dimm). the add on card might have a pull up or pull down. high drive pciclk and sdram outputs typically provide greater than 1 v/ns slew rate into 30pf loads. cpuclk outputs typically provide better than 1v/ns slew rate into 20pf loads while maintaining 505% duty cycle. the ref and 24 and 48 mhz clock outputs typically provide better than 0.5v/ns slew rates. pentium is a trademark of intel corporation i 2 c is a trademark of philips corporation ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ICS9148-08 pin descriptions notes: 1: internal pull-up resistor of 240k to 3.3v on indicated inputs 2: bidirectional input/output pins, input logic levels are latched at internal power-on-reset. use 10kohm resistor to program logic high to vdd or logic low to gnd. pin number pin name type description 1 vdd1 pwr ref (0:1), xtal power supply, nominal 3.3v 2 ref0 out 14.318 mhz reference clock. cpu3.3#_2.5 1,2 in indicates whether vddl2 is 3.3v or 2.5v. high=2.5v cpu, low=3.3v cpu 1 . latched input 2 3,9,16,22,27, 33,39,45 gnd pwr ground 4x1 in crystal input, has internal load cap (33pf) and feedback resistor from x2 5x2 out crystal output, nominally 14.318mhz. has internal load cap (33pf) 6,14 vdd2 pwr supply for pciclk_f and pciclk (0:5), nominal 3.3v 7 pciclk_f out free running pci clock fs1 1, 2 in frequency select pin. latched input 8 pciclk0 out pci clock output. fs2 1, 2 in frequency select pin. latched input 10, 11, 12, 13 pciclk(1:4) out pci clock outputs. 15 pciclk5 out pci clock output. (in desktop mode, mode=1) pci_stop# 1 in halts pciclk(0:5) clocks at logic 0 level, when input low (in mobile mode, mode=0) 17, 18, 20, 21, 28, 29, 31, 32, 34, 35,37,38 sdram (0:11) out sdram clock outputs. 19,30,36 vdd3 pwr supply for sdram (0:11), pll core and 24,48mhz clocks, nominal 3.3v 23 sdata in data input for i 2 c serial input. 24 sclk in clock input of i 2 c input 25 24mhz out 24mhz output clock mode 1, 2 in pin 15, pin 46 function select pin, 1=desktop mode, 0=mobile mode. latched input. 26 48mhz out 48mhz output clock fs0 1, 2 in frequency select pin. latched input 40, 41, 43, 44 cpuclk(0:3) out cpu clock outputs, powered by vddl2. low if cpu_stop#=low 42 vddl2 pwr supply for cpu (0:3), either 2.5v or 3.3v nominal 46 ref1 out 14.318 mhz reference clock, (in desktop mode, mode=1) this ref output is the stronger buffer for isa bus loads. cpu_stop# 1 in halts cpuclk (0:3) clocks at logic 0 level, when input low (in mobile mode, mode=0) 47 ioapic out ioapic clock output. 14.318 mhz powered by vddl1. 48 vddl1 pwr supply for ioapic, either 2.5 or 3.3v nominal
3 ICS9148-08 functionality v dd 1,2,3 = 3.3v5%, v ddl 1,2 = 2.5v5% or 3.35%, ta=0 to 70c crystal (x1, x2) = 14.31818mhz cpu3.3#_2.5 input level (latched data) buffer selected for operation at: 12.5v vdd 03.3v vdd cpu 3.3#_2.5v buffer selector for cpuclk and ioapic drivers. power management functionality fs2 fs1 fs0 cpu, sdram(mhz) pciclk (mhz) ref, ioapic (mhz) 0 0 0 50.0 25.0 (1/2 cpu) 14.318 0 0 1 75.0 30 (cpu/2.5) 14.318 0 1 0 83.3 33.3 14.318 0 1 1 68.5 34.25 (1/2 cpu) 14.318 1 0 0 55.0 27.5 (1/2 cpu) 14.318 1 0 1 75.0 37.5 (1/2 cpu) 14.318 1 1 0 60.0 30.0 (1/2 cpu) 14.318 1 1 1 66.8 33.4 (1/2 cpu) 14.318 mode pin - power management input control mode, pin 25 (latched input) pin 46 pin 15 0 cpu_stop# (input) pci_stop# (input) 1 ref1 (output) pciclk5 (output) cpu_stop# pci_stop# cpuclk outputs pciclk (0:5) pciclk_f, ref, 24/48mhz and sdram crystal osc vco 0 1 stopped low running running running running 1 1 running running running running running 1 0 running stopped low running running running
4 ICS9148-08 byte0: functionality and frequency select register (default = 0) serial configuration command bitmap general i 2 c serial interface information i 2 c is a trademark of philips corporation a. for the clock generator to be addressed by an i 2 c controller, the following address must be sent as a start sequence, with an acknowledge bit between each byte. b. the clock generator is a slave/receiver i 2 c component. it can "read back "(in philips i 2 c protocol) the data stored in the latches for verification. (set r/w# to 1 above). there is no byte count supported, so it does not meet the intel smb piix4 protocol. c. the data transfer rate supported by this clock generator is 100k bits/sec (standard mode) d. the input is operating at 3.3v logic levels. e. the data byte format is 8 bit bytes. f. to simplify the clock generator i 2 c interface, the protocol is set to use only block writes from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. g . in the power down mode (pwr_dwn# low), the sdata and sclk pins are tristated and the internal data latches maintain all prior programming information. h. at power-on, all registers are set to a default condition. see byte 0 detail for default condition, bytes 1 through 5 default to a 1 (enabled output state) then byte 0, 1, 2, etc in sequence until stop. byte 0, 1, 2, etc in sequence until stop. clock generator address (7 bits) ack + 8 bits dummy command code ack + 8 bits dummy byte count ack a(6:0) & r/w# d2 (h) clock generator address (7 bits) ack byte 0 ack byte 1 ack a(6:0) & r/w# d3 (h) note 1. default at power-up will be for latched logic inputs to define frequency. bits 4, 5, 6 are default to 000, and if bit 3 is written to a 1 to use bits 6:4, then these should be defined to desired frequency at same write cycle. note: pwd = power-up default bit description pwd bit 7 0 - 1.5% spread spectrum modulation 1 - 0.6% spread spectrum modulation 0 bit 6:4 bit6 bit5 bit4 111 110 101 100 011 010 001 000 cpu clock 66.8 60.0 75.0 55.0 68.5 83.3 75.0 50.0 pci 33.4(1/2 cpu) 30.0 (1/2 cpu) 37.5 (1/2 cpu) 27.5 (1/2 cpu) 34.5 (1/2 cpu) 33.3 30.0 (cpu/2.5) 25.0 (1/2 cpu) note1 bit 3 0 - frequency is selected by hardware select, latched inputs 1 - frequency is selected by bit 6:4 (above) 0 0 - spread spectrum center spread type. 1 - spread spectrum down spread type. 0 bit 1 0 - normal 1 - spread spectrum enabled 0 bit 0 0 - running 1- tristate all outputs 0
5 ICS9148-08 byte 1: cpu, active/inactive register (1 = enable, 0 = disable) byte 2: pci active/inactive register (1 = enable, 0 = disable) byte 3: sdram active/inactive register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. notes: 1. inactive means outputs are held low and are disabled from switching. 2. pciclk5 only in desktop mode notes: 1. inactive means outputs are held low and are disabled from switching. bit pin # pwd description bit 7 - 1 (reserved) bit 6 - 1 (reserved) bit 5 - 1 (reserved) bit 4 - 1 (reserved) bit 3 40 1 cpuclk3 (act/inact) bit 2 41 1 cpuclk2 (act/inact) bit 1 43 1 cpuclk1 (act/inact) bit 0 44 1 cpuclk0 (act/inact) bit pin # pwd description bit 7 - 1 (reserved) bit 6 7 1 pciclk_f (act/inact) bit 5 15 1 pciclk5 (act/inact) (desktop only) bit 4 14 1 pciclk4 (act/inact) bit 3 12 1 pciclk3 (act/inact) bit 2 11 1 pciclk2 (act/inact) bit 1 10 1 pciclk1 (act/inact) bit 0 8 1 pciclk0 (act/inact) bit pin # pwd description bit 7 28 1 sdram7 (act/inact) bit 6 29 1 sdram6 (act/inact) bit 5 31 1 sdram5 (act/inact) bit 4 32 1 sdram4 (act/inact) bit 3 34 1 sdram3 (act/inact) bit 2 35 1 sdram2 (act/inact) bit 1 37 1 sdram1 (act/inact) bit 0 38 1 sdram0 (act/inact) byte 4: sdram active/inactive register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. bit pin # pwd description bit 7 - 1 (reserved) bit 6 - 1 (reserved) bit 5 - 1 (reserved) bit 4 - 1 (reserved) bit 3 17 1 sdram11 (act/inact) bit 2 18 1 sdram10 (act/inact) bit 1 20 1 sdram9 (act/inact) bit 0 21 1 sdram8 (act/inact) byte 5: peripheral active/inactive register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. ref1 only in desktop mode bit pin # pwd description bit 7 - 1 (reserved) bit 6 - 1 (reserved) bit 5 - 1 (reserved) bit 4 47 1 ioapic0 (act/inact) bit 3 - 1 (reserved) bit 2 - 1 (reserved) bit 1 46 1 ref1 (act/inact) bit 0 2 1 ref0 (act/inact) bit pin # pwd description bit 7 - 1 (reserved) bit 6 - 1 (reserved) bit 5 - 1 (reserved) bit 4 - 1 (reserved) bit 3 - 1 (reserved) bit 2 - 1 (reserved) bit 1 - 1 (reserved) bit 0 - 1 (reserved) note: pwd = power-up default byte 6: optional register for possible future requirements notes: 1. byte 6 is reserved by integrated circuit systems for future applications.
6 ICS9148-08 cpu_stop# timing diagram cpu_stop# is an asychronous input to the clock synthesizer. it is used to turn off the cpu clocks for low power operation. cpu_stop# is synchronized by the ICS9148-08 . the minimum that the cpu clock is enabled (cpu_stop# high pulse) is 100 cpu clocks. all other clocks will continue to run while the cpu clocks are disabled. the cpu clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpu clock on latency is less than 4 cpu clocks and cpu clock off latency is less than 4 cpu clocks. notes: 1. all timing is referenced to the internal cpu clock. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpu clocks inside the ICS9148-08. 3. all other clocks continue to run undisturbed. (including sdram outputs).
7 ICS9148-08 notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9148 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics9148. 3. all other clocks continue to run undisturbed. 4. cpu_stop# is shown in a high (true) state. pci_stop# timing diagram pci_stop# is an asynchronous input to the ICS9148-08 . it is used to turn off the pciclk (0:5) clocks for low power operation. pci_stop# is synchronized by the ICS9148-08 internally. the minimum that the pciclk (0:5) clocks are enabled (pci_stop# high pulse) is at least 10 pciclk (0:5) clocks. pciclk (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. pciclk (0:5) clock on latency cycles are only one rising pciclk clock off latency is one pciclk clock.
8 ICS9148-08 pins 2, 7, 8, 25 and 26 on the ICS9148-08 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm(10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. figs. 1 and 2 show the recommended means of implementing this function. in fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the device?s internal logic. figs. 2a and b provide a single resistor loading option where either solder spot tabs shared pin operation - input/output pins fig. 1 or a physical jumper header may be used. these figures illustrate the optimal pcb physical layout options. these configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. the layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
9 ICS9148-08 fig. 2a fig. 2b
10 ICS9148-08 absolute maximum ratings supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.1 5 a input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 2 a input low current i il2 v in = 0 v; inputs with pull-up resistors -200 -100 a operating i dd3.3op c l = 0 pf; select @ 66mhz 100 160 ma supply current input frequency f i v dd = 3.3 v 12 14.318 16 mhz input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf transition time 1 t trans to 1st crossing of target freq. 2 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 2 ms skew 1 t cpu-sdram1 v t = 1.5 v 500 ps t cp u-p ci1 v t = 1.5 v 12.64ns 1 guaranteed by design, not 100% tested in production. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supp ly vo ltag e v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unles s otherwise stated) parameter symbol conditions min typ max units operating supply current i dd2.5op c l = 0 pf; select @ 66.8 mhz 8 20 ma skew 1 t cpu-sdram2 v t = 1.5 v; v tl = 1.25 v 800 ps t cpu-pci2 v t = 1.5 v; v tl = 1.25 v 14ps 1 guaranteed by design, not 100% tested in production.
11 ICS9148-08 electrical characteristics - cpu t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf parameter symbol conditions min typ max units output impedance 1 r dsp2b v o = v dd *(0.5) 13.5 45 ohm output impedance 1 r dsn2b v o = v dd *(0.5) 13.5 45 ohm output high voltage v oh2b i oh = -8 ma 2 2.2 v output low voltage v ol2b i ol = 12 ma 0.3 0.4 v output high current i oh2b v oh = 1.7 v -20 -16 ma output low current i ol2b v ol = 0.7 v 19 26 ma ris e time 1 t r2b v ol = 0.4 v, v oh = 2.0 v 2.2 2.5 ns fall time 1 t f2 b v oh = 2.0 v, v ol = 0.4 v 1.1 1.6 ns duty cycle 1 d t2b v t = 1.25 v 45 55 % skew 1 t sk2b v t = 1.25 v 250 ps jitter, cycle-to-cycle 1 t jcyc-cyc2b v t = 1.25 v 200 300 ps jitter, one sigma 1 t j1s2b v t = 1.25 v 50 150 ps jitter, absolute 1 t jabs2b v t = 1.25 v -250 +250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - pci t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 30 pf parameter symbol conditions min typ max units output impedance 1 r dsp1 v o = v dd *(0.5) 10 24 ohm output impedance 1 r dsn1 v o = v dd *(0.5) 10 24 ohm output high voltage v oh1 i oh = -28 ma 2.4 3 v output low voltage v ol1 i ol = 23 ma 0.2 0.4 v output high current i oh1 v oh = 2.0 v -60 -40 ma output low current i ol1 v ol = 0.8 v 41 50 ma ris e time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.6 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.2 2 ns duty cycle 1 d t1 v t = 1.5 v 45 51 55 % skew 1 t sk1 v t = 1.5 v 100 250 ps jitter, one sigma 1 t j1s1 v t = 1.5 v 100 300 ps jitter, absolute 1 t jabs1 v t = 1.5 v -500 500 ps 1 guaranteed by design, not 100% tested in production.
12 ICS9148-08 electrical characteristics - sdram t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 30 pf parameter symbol conditions min typ max units output impedance 1 r dsp1 v o = v dd *(0.5) 10 24 w output impedance 1 r dsn1 v o = v dd *(0.5) 10 24 w output high voltage v oh1 i oh = -28 ma 2.4 3 v output low voltage v ol1 i ol = 23 ma 0.2 0.4 v output high current i oh1 v oh = 2.0 v -60 -40 ma output low current i ol1 v ol = 0.8 v 41 50 ma ris e time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.6 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.2 2 ns duty cycle 1 d t1 v t = 1.5 v 45 52 55 % skew 1 t sk1 v t = 1.5 v 150 250 ps jitter, one sigma 1 t j1s1 v t = 1.5 v 50 150 ps jitter, absolute 1 t jabs1 v t = 1.5 v -250 +250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - ioapic t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf parameter symbol conditions min typ max units output impedance 1 r dsp4b v o = v dd *(0.5) 13.5 45 ohm output impedance 1 r dsn4b v o = v dd *(0.5) 13.5 45 ohm output high voltage v oh4b i oh = -8 ma 2 2.2 v output low voltage v ol4b i ol = 12 ma 0.3 0.4 v output high current i oh4b v oh = 1.7 v -20 -16 ma output low current i ol4b v ol = 0.7 v 19 26 ma ris e time 1 t r4b v ol = 0.4 v, v oh = 2.0 v 1.4 1.7 ns fall time 1 t f4 b v oh = 2.0 v, v ol = 0.4 v 1.3 1.6 ns duty cycle 1 d t4b v t = 1.25 v 50 60 % jitter, one sigma 1 t j1s4b v t = 1.25 v 1 3 % jitter, absolute 1 t jabs4b v t = 1.25 v -5 5 % 1 guaranteed by design, not 100% tested in production.
13 ICS9148-08 electrical characteristics - 24,48mhz, ref(0:1) t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 10 - 20 pf (unless otherwis e s tated) parameter symbol conditions min typ max units output impedance 1 r dsp5 v o = v dd *(0.5) 20 60 ohm output impedance 1 r dsn5 v o = v dd *(0.5) 20 60 ohm output high voltage v oh5 i oh = -16 ma 2.4 2.6 v output low voltage v ol5 i ol = 9 ma 0.3 0.4 v output high current i oh5 v oh = 2.0 v -32 -22 ma output low current i ol5 v ol = 0.8 v 16 25 ma ris e time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 1.7 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 1.6 4 ns duty cycle 1 d t5 v t = 1.5 v 45 53 55 % jitter, one sigma 1 t j1s5 v t = 1.5 v 1 3 % jitter, absolute 1 t jabs5 v t = 1.5 v 38% 1 guaranteed by design, not 100% tested in production.
14 ICS9148-08 ssop package ordering information ics9148f-08 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx f - ppp symbol common dimensions variations d n min. nom. max. min. nom. max. a .095 .101 .110 ac .620 .625 .630 48 a1 .008 .012 .016 a2 .088 .090 .092 b .008 .010 .0135 c.005- .010 d see variations e .292 .296 .299 e0.025 bsc h .400 .406 .410 h .010 .013 .016 l .024 .032 .040 n see variations 0 5 8 x .085 .093 .100 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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